In a semiconductor storage device such as a NAND flash EEPROM, selection gate transistors are conventionally provided on both ends of a memory cell array, respectively so as to select memory cells (a NAND string). While a hard mask for each gate electrode of a memory cell is processed by a sidewall transfer method for using a sidewall as a mask, a hard mask for each gate electrode of a selection gate transistor is processed by a lithographic technique. With the lithographic technique, the resolution for an aperiodic pattern such as a gate electrode pattern of the selection gate transistors is inferior to that for a periodic pattern such as a gate electrode pattern of the memory cell array. Therefore, it is necessary to design a semiconductor storage device so as to make a space width on a boundary between each selection gate transistor and a memory cell array larger than an interval between the adjacent memory cells.
However, if the space width between each selection gate transistor and a memory cell array is large, the following phenomenon occurs. At the time of processing gate electrodes of the selection gate transistors and those of the memory cells by RIE (Reactive Ion Etching), the phenomenon (substrate gouging) occurs that a semiconductor substrate is gouged out in a space region between each of the selection gate transistors and the memory cell array.
Such substrate gouging may cause a rise in a resistance of a diffusion layer and a reduction in a cell current in the space region between each selection gate transistor and the memory cell array.